CEA-Leti and Stanford Target Edge-Ai Apps with Breakthrough NVM Memory Cell

Paper at ISSCC 2019 Presents Proof-of-Concept Multi-Bit Chip that Overcomes NVM's Read/Write, Latency and Integration Challenges SAN FRANCISCO - Feb. Researchers at CEA-Leti and Stanford University have developed the world's first circuit integrating multiple-bit non-volatile memory (NVM) technology called Resistive RAM (RRAM) with silicon computing units, as well as new memory resiliency features that provide 2.3-times the capacity of existing RRAM. Target applications include energy-efficient, smart-sensor nodes to support artificial intelligence on the Internet of Things, or "edge AI". The proof-of-concept chip has been validated for a wide variety of applications (machine learning, control, security). Designed by a Stanford team led by Professors Subhasish Mitra and H.-S. Philip Wong and realized in CEA-Leti's cleanroom in Grenoble, France, the chip monolithically integrates two heterogeneous technologies: 18 kilobytes (KB) of on-chip RRAM on top of commercial 130nm silicon CMOS with a 16-bit general-purpose microcontroller core with 8KB of SRAM. The new chip delivers 10-times better energy efficiency (at similar speed) versus standard embedded FLASH, thanks to its low operation energy, as well as ultra-fast and energy-efficient transitions from on mode to off mode and vice versa.