CEA-Leti & Dolphin Design Report FD-SOI Breakthrough that Boosts Operating Frequency by 450% and Reduces Power Consumption by 30%

(c) CEA-P. Jayet J oin t Paper Presented at ISSCC 2021 Shows How New Adaptive Back-Biasing Technique O vercomes Integration Limits in Chip Design Flows CEA-Leti & Dolphin Design Report FD-SOI Breakthrough that Boosts Operating Frequency by 450% and Reduces Power Consumption by 30% . GRENOBLE, France - Feb. CEA-Leti and Dolphin Design have developed an adaptive back-biasing (ABB) architecture for FD-SOI chips that can be seamlessly integrated in the digital design flow with industrial-grade qualification, overcoming integration drawbacks of existing ABB techniques. Fully Depleted Silicon on Insulator (FD-SOI) is a technology that allows the biasing of the transistor's body that acts as a back gate. Unlike conventional bulk technology, FD-SOI enables a wide voltage range of the body bias. This permits compensating for process, voltage, and temperature (PVT) variations by controlling the threshold voltage.